Binary To Bcd Verilog

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4 bit binary to gray counter converter HDL Verilog Code

Binary To Bcd Conversion Verilog

The hundreds digit 1 is represented in binary by 0001. The tens digit 5 is represented in binary by 0101. The ones digit 9 is represented in binary by 1001. The entire number 159 in BCD is therefore: 01. The hundreds digit 1 is represented in binary by 0001. The tens digit 5 is represented in binary by 0101. The ones digit 9 is represented in binary by 1001. The entire number 159 in BCD is therefore: 01. Each shift effectively doubles the value of the binary number in the four bit shift register which is going to hold the converted BCD digit. Each time a bit is.

About Press Copyright Contact us Creators Advertise Developers Terms Privacy Policy & Safety How YouTube works Test new features Press Copyright Contact us Creators. The above logic is a single digit Binary to BCD converter, contained in the binarytobcddigit.vhd file. The higher level binarytobcd.vhd file instantiates one of these single digit converters for each digit of the BCD output and cascades them together to form a multi-digit Binary to BCD converter.

This page of verilog sourcecode covers 4 Bit Binary to Gray Counter Converter using verilog.

Symbol

Following is the symbol and truth table of 4 bit binary to gray counter converter.


Truth Table

Rst Clk En B3 B2 B1B0 G3 G2 G1 G0
1 X 0 0 0 0 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 1
0 1 1 0 0 1 0 0 0 1 1
0 1 1 0 0 1 1 0 0 1 0
0 1 1 0 1 0 0 0 1 1 0
0 1 1 0 1 0 1 0 1 1 1
0 1 1 0 1 1 0 0 1 0 1
0 1 1 0 1 1 1 0 1 0 0
0 1 1 1 0 0 0 1 1 0 0
0 1 1 1 0 0 1 1 1 0 1
0 1 1 1 0 1 0 1 1 1 1
0 1 1 1 0 1 1 1 1 1 0
0 1 1 1 1 0 0 1 0 1 0
0 1 1 1 1 0 1 1 0 1 1
0 1 1 1 1 1 0 1 0 0 1
0 1 1 1 1 1 1 1 0 0 0

Verilog code


module b2g(b,g);
input [3:0] b;
output [3:0] g;
xor (g[0],b[0],b[1]),
(g[1],b[1],b[2]),
(g[2],b[2],b[3]);
assign g[3]=b[3];
end module

Simulation result


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Computers understand binary number system while humans areused to arithmetic operations in decimal number systems. To enhanceComputer-Human relationship in this perspective, arithmetic operations areperformed by the computer in a binarycoded decimal, (BCD) form.
In this article I’ll analyse and design a BCD adder whichrequires a minimum of nine inputs and five outputs, four bits are require tocode the aguend and the addend making eight bits, and the circuit input carrymakes the nine inputs. The four bit sum output and the output carry representsthe five outputs.

Binary To Bcd Conversion Verilog Code

Consider adding 9+9+1 in decimal, the result is 19, instraight binary this should produce an output 100112, this is aninvalid number in BCD, because in BCD code the group of four bit binary onlyrepresent decimal numbers 0-9. The table bellow shows decimal numbers 0-19 withtheir corresponding binary and BCD codes. The K and C in the table are therespective binary carry and BCD carry bits.

Bellow the ruled level on the table, the BCD adder should detectthat the binary codes are unusable in BCD coding system and provide thenecessary correction. The conditions for the levels on the table wherecorrection is required a;
  1. Point where binary sum has output carry K =1 or,
  2. where Z8 and Z2 are both = 1 or,
  3. where Z8 and Z4 are both = 1.
The gives the expression for correction requirement: Cor = K + Z8Z4+Z8Z2
When Cor = 1, it is necessary to add 0110 to the binary sumand provide an output carry for the next stage.



















Figure 1: Block diagram of BCD adder

Binary To Bcd Verilog

Binary To Bcd Verilog
When an output carry K = 0 nothing happens as the out S8S4S2S1 is added to 0000 in the second4-bit adder, but when K=1 OR Z8&Z4 OR Z8&Z2 is equal to ‘1’, the output carry generates a ‘1’, thus “0110”is added to the output of the first 4-bit adder. The MSB 0 and LSB 0 in the“0110” to be added is generate by the EXOR gate which accept the output carryat its two input, either the output carry is 0 or 1 the EXOR generates a ‘0’(both its input are equal).
The CBCD is the carry generated by the BCD adder,whenever the output of the OR-gate is ‘1’ a carry is generated by the BCD adderto the next four-bit group of the BCD code, carry output generated by the 4-bit adder of the second stage is discarded as it will provided by CBCD as required. Bellow is the Verilog HDL code forBCD adder and figure 2,3, and four shows the simulations changing the bitsvalue at 100ns, 200ns and 300ns.
//-----------------------------------------------------
input [3:0] A, B;

Bcd
output C;
wire C1, C2, C3, C4,C5;
and (C1, Z[3], Z[2]);
or (C, C3, C1,C2);

assign X[1] = C;
assign X[0] = C5;

four_bit_adder F_1 (Z,C3, A, B, C0);

//----------------------------------------------------------

//-------------------------------------------------------------
// Test bench forBCD_Adder
wire [3:0] S;
reg [3:0]A, B;


Binary to bcd converter verilog
begin
#100 A[3:0] = 4'b1000;B = 4'b0011; C0 = 1'b0;

Binary To Bcd Converter Verilog

initial #400 $finish;
//--------------------------------------------

16 Bit Binary To Bcd Verilog Code












Figure 2:Simulation showing the initial bits value of A: 0000, B: 0000, Sum S: 0000 andCarry C: 0 for the BCD adder (i.e. 0 + 0 = 0 0).












Figure 3:Simulation showing the bits value at 100ns for A: 1001, B: 1001, Sum S: 1000 and Carry C: 1 for the BCD adder (i.e. 9 +9 = 1 8 ).











Figure 4:Simulation showing the bits value at 300ns for A: 1000, B: 0011, Sum S: 0001 and Carry C: 1 for the BCD adder (i.e. 8+3 = 1 1 ).

Figure 5:Simulation showing the bits value at 300ns for A: 0100, B: 0011, Sum S: 0111 and Carry C: 0 for the BCD adder (i.e. 4+3 = 0 7 ).
Reference
Mano M. Morris andCiletti D. Michael; “Digital Design With and Introduction to the VerilogHDL – Fifth Edition” Copyright © 2013, 2007, 2002, 1991, 1984 Person Education,Inc., publishing as Prentice Hall, One Lake Street, Upper Saddle River, NewJersey 07458.